FPGA Design Digest

Home
Notes
Archive
About
Musings in SystemVerilog
Exploring the Intricacies of Blocking and Non-Blocking Assignment Statements
 • 
Milind Parelkar
Designing with Xilinx Memory Primitives: Understanding Inference vs Instantiation
Utilizing XPMs for Enhanced Memory Management and Portability
 • 
Milind Parelkar
An Introduction to Xilinx FPGA Memory Primitives
Practical Insights into BlockRAM, Distributed RAM, and UltraRAM
 • 
Milind Parelkar
Vim Tips and Tricks for RTL Designers #1
Code Alignment Made Easy
 • 
Milind Parelkar
1
The Magic of Gray Codes in Digital Circuits
How Gray Codes Enhance Accuracy and Reliability in Digital Design
 • 
Milind Parelkar
Control Sets Demystified
Tips, Tricks and Best Practices
 • 
Milind Parelkar
Interview Insights: Tackling Basic FPGA Design Challenges
A Simple Pulse Generator Design
 • 
Milind Parelkar
Rethinking Resets: Best Practices for FPGA Design
Balancing Initialization and Performance in FPGAs
 • 
Milind Parelkar
FPGA Design Digest
FPGA Design Digest
A series of write-ups delving into nuances of RTL and FPGA design
Recommendations
Vik's Newsletter
Vik's Newsletter
Vikram Sekar

FPGA Design Digest

AboutArchiveRecommendationsSitemap
© 2024 Milind Parelkar
Privacy ∙ Terms ∙ Collection notice
Start WritingGet the app
Substack is the home for great culture